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ECLSOIC8EVB Evaluation Board Manual for High Frequency SOIC 8
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EVALUATION BOARD MANUAL
INTRODUCTION ON Semiconductor has developed an evaluation board for the devices in 8-lead SOIC package. These evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 8-lead SOIC device samples. The board provides a high bandwidth 50 W controlled impedance environment. The pictures in Figure 1 show the top and bottom view of the evaluation board, which can be configured in several different ways, depending on device under test (See Table 1. Configuration List). This evaluation board manual contains: * Information on 8-lead SOIC Evaluation Board * Assembly Instructions * Appropriate Lab Setup * Bill of Materials This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation.
Board Lay-Up
The 8-lead SOIC evaluation board is implemented in four layers with split (dual) power supplies (Figure 2. Evaluation Board Lay-up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 W internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008 thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground plane and a portion of the plane is the VEE power plane. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is also 1.0 oz copper ground plane and a portion of this layer is VCC power plane. The fourth layer is the secondary trace layer.
Figure 1. Top and Bottom View of the 8-lead SOIC Evaluation Board
(c) Semiconductor Components Industries, LLC, 2004
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August, 2004 - Rev. 1
Publication Order Number: ECLSOIC8EVB/D
ECLSOIC8EVB
LAY-UP DETAIL 4 LAYER SILKSCREEN (TOP SIDE) 0.062 $ 0.007
LAYER 1 (TOP SIDE) ROGERS 4003 0.008 in LAYER 2 (GROUND AND VEE PLANE P1) 1 OZ FR-4 0.020 in LAYER 3 (GROUND AND VCC PLANE P2) 1 OZ FR-4 0.025 in LAYER 4 (BOTTOM SIDE)
Figure 2. Evaluation Board Lay-up Board Layout
The 8-lead SOIC evaluation board was designed to be versatile and accommodate several different configurations. The input, output, and power pin layout of the evaluation board is shown in Figure 3. The evaluation board has at least eleven possible configurable options. Table 1. list the
devices and the relevant configuration that utilizes this PCB board. List of components and simple schematics are located in Figures 4 through 14. Place SMA connectors on J1 through J7, 50 W chip resistors on R1 through R7, and chip capacitors C1 through C4 according to configuration figures. (C1 and C2 are 0.01 mF and C3 and C4 are 0.1 mF).
Top View
Bottom View
Figure 3. Evaluation Board Layout
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Table 1. Configuration List
ECLinPS LiteE Device MC10EL01D/MC100EL01D MC10EL04D/MC100EL04D MC10EL05D/MC100EL05D MC10EL07D/MC100EL07D MC10EL11D/MC100EL11D MC10EL12D/MC100EL12D MC10EL16D/MC100EL16D* MC10EL31D/MC100EL31D MC10EL32D/MC100EL32D MC10EL33D/MC100EL33D MC10EL35D/MC100EL35D MC10EL51D/MC100EL51D MC10EL52D/MC100EL52D MC10EL58D/MC100EL58D MC10EL89D/MC100EL89D MC10ELT20D/ MC100ELT20D MC10ELT21D/ MC100ELT21D MC10ELT22D/ MC100ELT22D MC100ELT23D MC10ELT26D/ MC100ELT26D MC10ELT28D/ MC100ELT28D Comments See Figure 4 See Figure 5 See Figure 4 See Figure 5 See Figure 6 See Figure 6 See Figure 5 See Figure 4 See Figure 7 See Figure 7 See Figure 4 See Figure 4 See Figure 4 See Figure 8 See Figure 6 See Figure 9 See Figure 10 See Figure 11 See Figure 12 See Figure 13 See Figure 14 Configuration 1 2 1 2 3 3 2 1 4 4 1 1 1 5 3 6 7 8 9 10 11 MC100EP16FD* MC10EP16TD/ MC100EP16TD* MC100EP16VAD* MC100EP16VBD* MC100EP16VCD* MC100EP16VSD* MC100EP16VTD* MC10EP31D/MC100EP31D MC10EP32D/MC100EP32D MC10EP33D/MC100EP33D MC10EP35D/MC100EP35D MC10EP51D/MC100EP51D MC10EP52D/MC100EP52D MC10EP58D/MC100EP58D MC100EP89D MC10EPT20D/ MC100EPT20D MC100EPT21D* MC100EPT22D Low Voltage ECLinPSE Device MC100LVEL01D MC100LVEL05D MC100LVEL11D MC100LVEL12D MC100LVEL16D* MC100LVEL31D MC100LVEL32D MC100LVEL33D MC100LVEL51D MC100LVEL58D MC100LVELT22D MC100LVELT23D Comments See Figure 4 See Figure 4 See Figure 6 See Figure 6 See Figure 5 See Figure 4 See Figure 7 See Figure 7 See Figure 4 See Figure 8 See Figure 11 See Figure 12 Configuration 1 1 3 3 2 1 4 4 1 5 8 9 NB6L11D NB6L16D Device ECLinPS MAXE Comments See Figure 6 See Figure 5 Configuration 3 2 MC100LVEP11D MC100LVEP16D* Low Voltage ECLinPS Plus Device Comments See Figure 6 See Figure 5 Configuration 3 2 MC100EPT23D* MC100EPT26D* See Figure 5 See Figure 5 See Figure 5 See Figure 5 See Figure 8 See Figure 5 See Figure 5 See Figure 4 See Figure 7 See Figure 7 See Figure 4 See Figure 4 See Figure 4 See Figure 8 See Figure 6 See Figure 9 See Figure 10 See Figure 11 See Figure 12 See Figure 13 2 2 2 2 5 2 2 1 4 4 1 1 1 5 3 6 7 8 9 10 Device MC10EP01D/MC100EP01D MC10EP05D/MC100EP05D MC10EP08D/MC100EP08D MC10EP11D/MC100EP11D MC10EP16D/ MC100EP16D* ECLinPS PlusE Comments See Figure 4 See Figure 4 See Figure 4 See Figure 6 See Figure 5 Configuration 1 1 1 3 2
*See Appendix for additions or modifications to the current configuration.
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Evaluation Board Assembly Instructions The 8-lead SOIC evaluation board is designed for characterizing devices in a 50 W laboratory environment using high bandwidth equipment. Each signal trace on the board has a via, which has an option of termination resistor or bypassing capacitor depending on the input/output configuration (see Table 1. Configuration List). Table 17 contains the Bill of Materials for this evaluation board.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or soldering re-flow techniques. Make sure pin 1 of the device is located next the white dotted mark U1 and all the pins are aligned to the footprint pads. Solder the 8-lead SOIC device to the evaluation board.
Connecting Power and Ground Planes
On the top side of the evaluation board solder the four surface mount test point clips to the pads labeled VCC, VEE, and GND. The VCC clip connects directly to pin 8 of the device. The VEE clip connects directly to pin 5 of the device. There are two GND clip footprints which can be connected to the ground plane of the evaluation board depending on the setup configuration. It is recommended to solder 0.01 mF capacitors to C1 and C2 to reduce the unwanted noise from the power supplies. C3 and C4 pads are provided for 0.1 mF capacitor to further diminish the noise from the power supplies. Adding capacitors can improve edge rates, reduce overshoot and undershoot.
Termination
For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC - 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is -3.0 V or -1.3 V; see Table 2: Power Supply Levels).
Table 2. Power Supply Levels
Power Supply 5.0 V 3.3 V 2.5 V VCC 2.0 V 2.0 V 2.0 V VEE -3.0 V -1.3 V -0.5 V GND 0.0 V 0.0 V 0.0 V
All ECL outputs need to be terminated to VTT (VTT = VCC -2.0 V = GND) via a 50 W resistor in a split power supply lab set-up. 0603 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver (More information on termination is provided in AN8020). Solder the chip resistors to the bottom side of the board on the appropriate input of the device pins labeled R1, R2, R3, R4, R6, and R7, depending on the specific device.
Installing the SMA Connectors
The power supply for voltage level translating device need slight modification as indicated in Table 3. Power Supply Levels for Translators.
Table 3. Power Supply Levels for Translators
VCC PECL Translators 3.3 V / 5.0 V VEE 0.0 V GND 0.0 V
Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given configuration. Each input and output requires one SMA connector. Attach all the required SMA connectors onto the board and solder the connectors to the board. Please note that alignment of the signal connector pin of the SMA can influence the lab results. The reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the SMA connector.
Validating the Assembled Board
After assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. Time Domain Reflectometry (TDR) is another highly recommended validation test.
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CONFIGURATIONS
VCC GND
C4 0.1 mF
R1 50 W J1 R2 50 W J2 R3 50 W J3 R4 50 W J4
C1 0.01 mF
DUT J5
C2 0.01 mF
J6
C3 0.1 mF VEE GND
Figure 4. Configuration 1 Schematic
Table 4. Configuration 1
Pin 1 Device MC10EL01D/MC100EL01D MC10EL05D/MC100EL05D MC10EL31D/MC100EL31D MC10EL35D/MC100EL35D MC10EL51D/MC100EL51D MC10EL52D/MC100EL52D MC100LVEL01D MC100LVEL05D MC100LVEL31D MC100LVEL51D MC10EP01D/MC100EP01D MC10EP05D/MC100EP05D MC10EP08D/MC100EP08D MC10EP31D/MC100EP31D MC10EP35D/MC100EP35D MC10EP51D/MC100EP51D MC10EP52D/MC100EP52D Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 R2 50 W J2 R3 50 W J3 Pin 4 J4 (Optional) Pin 5 C3 0.1 mF VEE GND Pin 3 Pin 6 C2 0.01 mF J6 Pin 7 DUT J7
Figure 5. Configuration 2 Schematic
Table 5. Configuration 2
Pin 1 Device MC10EL04D/MC100EL04D MC10EL07D/MC100EL07D MC10EL16D/MC100EL16D* MC100LVEL16D* MC10EP16D/MC100EP16D* MC100EP16FD* MC100LVEP160* MC10EP16TD/MC100EP16TD* MC100EP16VAD* MC100EP16VBD* MC100EP16VSD* MC100EP16VTD* NB6L160D *See Appendix for additional or modification to the current configuration No No Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 Pin 7 DUT J2 Pin 3 J3 Pin 4 J4 Pin 5 C3 0.1 mF VEE GND Pin 6 R6 50 W R7 50 W J7
J1
C2 0.01 mF
J6
Figure 6. Configuration 3 Schematic Table 6. Configuration 3
Pin 1 Device MC10EL11D/MC100EL11D MC10EL12D/MC100EL12D MC10EL89D/MC100EL89D MC100LVEL11D MC100LVEL12D MC10EP11D/MC100EP11D MC100EP89D MC100LVEP11D NB6L11D Yes No Yes No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 Pin 7 DUT J7 Pin 3 R3 50 W J3 Pin 4 Pin 5 Pin 6 C2 0.01 mF
R1 50 W J1 R2 50 W J2
J6
J4 (Optional)
C3 0.1 mF VEE GND
Figure 7. Configuration 4 Schematic Table 7. Configuration 4
Pin 1 Device MC10EL32D/MC100EL32D MC10EL33D/MC100EL33D MC100LVEL32D MC100LVEL33D MC10EP32D/MC100EP32D MC10EP33D/MC100EP33D Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF R2 50 W J2 R3 50 W J3 R4 50 W J4 (Optional) C3 0.1 mF VEE GND Pin 3 Pin 6 C2 0.01 mF J6 Pin 2 Pin 7 DUT J7
Pin 4
Pin 5
Figure 8. Configuration 5 Schematic Table 8. Configuration 5
Pin 1 Device MC100EP16VCD* MC10EL58D/MC100EL58D MC100LVEL58D MC10EP58D/MC100EP58D *See Appendix for addition or modification to the current configuration No No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 J2 Pin 3 J3 Pin 4 Pin 5 Short Pin 6 Pin 7 DUT R7 50 W (optional) J7
VEE
GND
Figure 9. Configuration 6 - Translator Schematic Table 9. Configuration 6
Pin 1 Device MC10ELT20D/MC100EL20D MC10EPT20D/MC100EPT20D No No Yes No Yes No No No No No No No Yes Optional Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 J7 Pin 7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF R2 50 W J2 R3 50 W J3 Pin 4 Pin 5 Short Pin 3 Pin 6 Pin 2 Pin 7 DUT J7
VEE
GND
Figure 10. Configuration 7 - Translator Schematic (Unloaded Testing Condition) Table 10. Configuration 7
Pin 1 Device MC10ELT21D/MC100EL21D MC100EPT21D *See Appendix for loaded testing condition. No No Yes Yes Yes Yes No No No No No No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 J1 Pin 2 J2 Pin 3 J3 Pin 4 J4 VEE Pin 5 Pin 6 Pin 7 DUT Pin 8 C1 0.01 mF R7 50 W (optional) J7 R6 50 W (optional) J6 Short
GND
Figure 11. Configuration 8 - Translator Schematic Table 11. Configuration 8
Pin 1 Device MC10ELT22D/ MC100EL22D MC100LVELT22D MC100EPT22D Yes Y No N Yes Y No N Yes Y No N Yes Y No N No N No N Yes Y Optional O ti l Yes Y Optional O ti l Yes Y Yes Y J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 J6 Pin 6 R6 J57 Pin 7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 Pin 7 DUT J7 R3 50 W J3 R4 50 W J4 VEE Pin 4 Pin 5 Short Pin 3 Pin 6 J6
R1 50 W J1 R2 50 W J2
GND
Figure 12. Configuration 9 - Translator Schematic (Unloaded Testing Condition) Table 12. Configuration 9
Pin 1 Device MC100EL23D MC100LVELT23D MC100EPT23D *See Appendix for loaded testing condition. Yes Yes Yes Yes Yes Yes Y Yes Yes No No Yes No Yes No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 R7 Pin 8 C1 C4
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF R2 50 W J2 R3 50 W J3 Pin 4 Pin 5 Short Pin 3 Pin 6 J6 Pin 2 Pin 7 DUT J7
VEE
GND
Figure 13. Configuration 10 - Translator Schematic (Unloaded Testing Condition) Table 13. Configuration 10
Pin 1 Device MC10ELT26D/MC100ELT26D MC100EPT26D *See Appendix for loaded testing condition. No No Yes Yes Yes Yes No No No No Yes Yes J1 R1 Pin 2 J2 R2 Pin 3 J3 R3 Pin 4 J4 R4 Pin 5 C2 C3 Pin 6 J6 R6 Pin 7 J7 Yes R7 No Pin 8 C1 Yes C4 Yes
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VCC GND
C4 0.1 mF Pin 1 Pin 8 C1 0.01 mF Pin 2 Pin 7 DUT J7 Pin 3 J3 Pin 4 J3 VEE GND Pin 5 Short Pin 6 R6 50 W (optional)
R1 50 W J2 R2 50 W J2
J6
Figure 14. Configuration 11 - Translator Schematic Table 14. Configuration 11
Pin 1 Device MC10ELT28D/MC100ELT28D J1 Yes R1 Yes Pin 2 J2 Yes R2 Yes Pin 3 J3 Yes R3 No Pin 4 J4 Yes R4 No Pin 5 C2 No C3 No J6 Yes Pin 6 R6 Optional Pin 7 J7 Yes R7 No Pin 8 C1 Yes C4 Yes
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LAB SETUP
Power Supply VCC OUT1 J1 Test Measuring Equipment J7 Channel 1 GND
J2 OUT1
Differential Signal Generator DUT OUT2 J3 J4 J6 Channel 2
OUT2 TRIGGER VEE GND TRIGGER
Power Supply
Figure 15. Example of Standard Lab Setup (Configuration 1)
1. Connect appropriate power supplies to VCC, VEE, and GND. For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC - 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is -3.0 V or -1.3 V; see Table 15).
Table 15. Power Supply Levels
Power Supply 5.0 V 3.3 V 2.5 V VCC 2.0 V 2.0 V 2.0 V VEE -3.0 V -1.3 V -0.5 V GND 0.0 V 0.0 V 0.0 V
The power supply for voltage level translating device need slight modification as indicated in Table 16.
Table 16. Power Supply Levels for Translators
VCC PECL Translators 3.3 V / 5.0 V VEE 0.0 V GND 0.0 V
2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. 3. Connect a test measurement device on the device output SMA connectors. NOTE: The test measurement device must contain 50 W termination.
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Table 17. Bill of Materials
Components SMA Connector Manufacturer Rosenberger Johnson Components* Surface Mount Test Points Keystone* Description SMA Connector, Side Launch, Gold Plated SMA Connector, Side Launch, Gold Plated SMT Miniature Test Point SMT Compact Test Point Thru-Hole Mount Compact Test Point Chip Capacitor AVC Corporation* 0603 0.01 mF 10% 0603 0.1 mF 10% Chip Resistor Evaluation Board Device Samples Vishay Dale* ON Semiconductor ON Semiconductor 0603 50 W 1% Thick Film Resistor SOIC 8 Evaluation Board SOIC 8 Package Device Part Number 32K243-40ME3 142-0701-851 5015 5016 5005-5009 06035C103KAT2A 06035C104KAT2A CRCW060351R1J ECLSOIC8EVB Various http://www.vishay.com http://www.onsemi.com http://www.onsemi.com http://www.avxcorp.com Web Site http://www.rosenberger.de http://www.rosenbergerna.com http://www.johnsoncomponents.com http://www.keyelco.com
*Components are available through most distributors, i.e. www.newark.com, www.digikey.com
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Appendix A (Modified Configurations) MC10EL16D/MC100EL16D MC100LVEL16D MC10EP16D/MC100EP16D MC10EP16DF/MC100EP16DF MC100EP16VAD MC100LVEP16D MC100EP16VSD
The devices listed above have the option of being driven single-endedly by using the provided VBB pin of the device. In order to drive it single-endedly, Configuration 2 needs to be modified. 1. Remove the 50 W chip resistor from R3. 2. Short pin 3 and pin 4 together. Option A) Short R3 and R4 trace pads. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors.
MC10EP16D/MC100EP16DT
This device has an option of varying the output swing amplitude and being driven single-endedly. In order to utilize these options, Configuration 2 needs to be modified. Output Swing Control 1. Connect a SMA connector on J1 2. Add a decoupling capacitor between J1 and VCC (0.01 mF) Drive Single-Endedly 1. Remove the 50 W chip resistor from R3. 2. Short pin 3 and pin 4 together. Option A) Short R3 and R4. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors.
MC100EP16VTD
This device has an option of being 50 W terminated internally. To evaluate the internal 50 W resistor of the device, Configuration 2 needs to be modified. 1. Remove the 50 W chip resistors from R2 and R3. 2. Short R1 and R4 to VTT (GND). Option A) Short R1 and R4 to VTT (GND). Or Option B) Place SMA connectors on J1 and J4. Place shorting barrels on J1 and J4 SMA connector.
MC100EP16VBD
This device has an option of single-ended feedback output and being driven single-endedly using the VBB. To utilize the feedback option and drive it single-endedly, Configuration 2 needs to be modified. Feedback option 1. Connect a SMA connector on J1 Drive single-endedly 2. Remove the 50 W chip resistor from R3. 3. Short pin 3 and pin 4 together. Option A) Short R3 and R4. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors.
MC100EP16VCD
This device has an option of varying the output swing amplitude and internal termination. In order to utilize these options, Configuration 2 needs to be modified. Output Swing Control 1. Connect a SMA connector on J1 2. Add a decoupling capacitor between J1 and VCC (0.0 1 mF) Internal Termination 1. Remove the 50 W chip resistors from R2 and R3. 2. Short R1 and R4 to VTT (GND) Option A) Short R1 and R4 to VTT (GND). Or Option B) Place SMA connectors on J1 and J4. Place shorting barrels on J1 and J4 SMA connector.
MC10ELT21D/MC100EL21D MC100EL23D MC10ELT26D/MC100ELT26D MC100EPT21D MC100EPT23D MC100EPT26D MC100LVELT23
This device has an option of single-ended feedback output with an enable pin. To utilize the feedback option and enable option, Configuration 5 needs to be modified. 1. Connect a SMA connector on J1. 2. Remove the 50 W chip resistor from R3.
The TTL output data presented in the data sheet are obtained under 500 W load resistor in parallel with 20 pF fixture capacitance. In order to obtain comparable data as in the data sheet, the evaluation board needs to be modified. 1. Cut the output trace so that the 0402* size chip resistor can be placed over the cut out trace. 2. Solder a 450 W chip resistor across the cut out trace.
*Any size chip resistor can be used. The recommended size of the chip resistor is 0402, to reduce the effect of parasitic with a 17 mil trace width. 450 W in series with 50 W instrument resistance add up to 500 W loaded condition.
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Appendix B (Gerber Files)
Top Layer
Second Layer (VEE and Ground Plane
Third Layer (VCC and Ground Plane)
Bottom Layer
Figure 16. Gerber Files
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ECLinPS, ECLinPS Lite, ECLinPS Plus, and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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